1. Field of the Invention
An embodiment of the present invention relates to the fabrication of interconnect structures in microelectronic devices. In particular, embodiments of the present invention relate to utilizing a coupling agent complexed with a catalytic metal and electroless deposition to form conformal barrier material layers.
2. State of the Art
The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the electrical components to form integrated circuits. The metallization patterns are generally referred to as “interconnects”.
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a dielectric material and the dielectric material is etched through the photoresist material patterning to form a hole or a trench (hereinafter collectively referred to as “an opening” or “openings”). The photoresist material is then removed (typically by an oxygen plasma) and the opening is then filled with a conductive material (e.g., such as a metal or metal alloys). The filling of the opening may be accomplished by either physical vapor deposition, chemical vapor deposition, or electroplating, as will be understood to those skilled in the art. When the opening is a hole, the resulting filled structure is referred to herein as a “via”. When the opening is a trench, the resulting filled structure is referred to herein as a “filled trench”. The term “interconnect” is defined herein to include all interconnection components including filled trenches and vias.
Generally, a barrier material layer is deposited on the dielectric material within the opening prior to the deposition of the conductive material to prevent diffusion of a conductive material into the dielectric material. The barrier material layers are formed by depositing barrier material, such as tantalum nitride/tantalum and the like, using a physical vapor deposition (“PVD”) sputtering technique. Sputtering is a physical process wherein atoms in a solid target material are ejected into a gas phase due to bombardment of the target by ions. The ions are generated by a plasma that is struck within a sputtering chamber. The ejected ions are then deposited on a substrate (i.e., the dielectric material), which is placed in the sputtering chamber.
Once the barrier material layer is formed, a conductive material is deposited in the opening usually with the assistance of a seed layer deposited on the barrier material layer prior to the deposition of the conductive material. The conductive material may be deposited by any technique known in the art, including but not limited to physical vapor deposition, chemical vapor deposition, electroless, and electroplating. The resulting structure is planarized, such as by chemical mechanical polishing or by an etching process, which removes the conductive material, which is not within the opening, from the surface of the dielectric material, to form the interconnect. Of course, a variety of vias and filled trenches may be formed in the various dielectric material layers to electrically connect to one another and/or to various electronic components. In another damascene process, known as a “dual damascene process”, trenches and vias are substantially simultaneously filled with the conductive material with a single deposition.
As the density of integrated circuits within microelectronic devices continues to increase with each successive technology generation, the interconnects become smaller and their aspect ratios (i.e., the ratio of depth to width) increases. As shown in FIGS. 9 and 10, a problem with small size and/or high aspect ratios is that the sputtering process used to form the barrier material 302 can build up at an opening 304 proximate a first surface 306 of a dielectric material 308 (i.e., the “mouth” 310 of the opening 304) during deposition. This barrier material build-up is a natural consequence of the “line-of-sight” nature of the sputtering process, as will be understood to those skilled in the art.
A conductive material 312 is then deposited by electroplating; however, the build-up (illustrated within dashed circle 314 in FIGS. 9 and 10) blocks the path of the deposited conductive material 312 and, as shown in FIG. 11, can result in voids 316 forming within the conductive material 312 in the opening 304 (shown in FIGS. 9 and 10). FIG. 11 illustrates an interconnect 318 formed after the conductive material 312, which is not within the opening 304 (shown in FIGS. 9 and 10), from the dielectric material first surface 306. The voids 316 can have different sizes, distributions, and locations within the interconnect 318. For example, some voids 316 may be so large that they effectively break the conductive path of the interconnect 318, which may result in the failure of the microelectronic device, thereby having an immediate yield impact. Additionally, the voids 316 may also be small, which may have an immediate impact by restricting the flow of electrons along the interconnect 318 and/or may have a negative impact on the long-term reliability of the microelectronic device. Additionally, direct electroplating of the barrier materials is not an attractive option due to the large voltage drop across of the wafer and the weak adhesion strength between the air oxidized barrier material and the conductive material, such as copper, as will be understood to those skilled in the art.
Therefore, it would be advantageous to develop techniques and materials to deposit barrier material layers such that barrier material layer build-up at the entrance of the features is reduced or substantially eliminated, which thereby reduces or substantially eliminates void formation during the fabrication of interconnects for microelectronic devices.